Method of making mosfet by multiple implantations followed by a diffusion step

ABSTRACT

A short channel metal oxide semiconductor transistor device is processed without undesirable short channel effects, such as V T  falloff and with a reasonable source-drain operating voltage support. In a substrate lightly doped with P-type conductivity material and source and drain region heavily doped with an N-type conductivity material, two lightly doped N- regions are disposed between the edge of the gate and the source and drain regions. A channel region is more heavily doped with P-type material than the substrate. Two regions extend from opposite sides of the channel region to an area generally below the two N- regions and above the substrate, which regions are more heavily doped than the channel regions.

This is a division of application Ser. No. 335,608, filed Dec. 30, 1981,now abandoned.

TECHNICAL FIELD

The present invention relates to a metal oxide semiconductor device anda process for fabricating such a device, more particularly to fieldeffect transistors used in large scale integrated circuits and a processfor fabricating such devices.

BACKGROUND OF THE INVENTION

Process and device technology have been developed to improve theperformance of large scale integrated circuits. Increasing the densityof MOS devices and LSI circuits result in improved higher speeds ofoperation.

Nonplanar-type devices have been proposed for such high performance LSIcircuits, including a nonplanar diffusion self-aligned (DSA) MOStransistor and a VMOS transistor. These two nonplanar devices have threedimensional configurations, which increase the packing density of theLSI. However, the process for fabricating such devices include anepitaxial and a V-groove process which require a larger number offabrication steps than that of the planar-type devices.

Planar-type devices utilized for high performance LSI circuits havegenerally involved scaling down the physical dimensions of thetransistor. The short channel lengths involved in such scaled downtransistors have involved limitations from the electricalcharacteristics present in such scaled down devices. The limitations onsuch short channel device have been the following: limited drainvoltage, threshold voltage (V_(T)) falloff, and impact ionization in thedrain pinchoff region. The drain voltage is limited by punch-throughvoltage decrease, snap back and gate field plated P-N junction avalanchebreakdown. The threshold voltage falloff is limited by the drain fieldinduced barrier lowering and the drain and source junction dopingprofile and substrate doping concentration. The impact ionization in thedrain pinchoff region leads to hot-electron injection into the gateoxide and the substrate electron current due to secondary impactionization.

There have been several approaches in device structures and fabricationtechnologies to remove some of these limitations. One fabricationtechnology uses a high resistivity substrate and double channelimplants, where a deep implant is used to increase the punch-throughvoltage and a shallow implant is used to control V_(T). A secondapproach has been a diffusion self-aligned MOS transistor or adouble-diffused MOS transistor. This device causes double diffusion ofP-type impurities from the same diffusion window, the process yieldsgood short channel V_(T) falloff and a source-drain breakdown control.Yet a third approach has been a lightly doped drain-source (LDD) processand a quadruply self-aligned (QSA) process. The LDD structure introducesnarrow, self-aligned N-regions between the channel and the N+source-drain diffusions of an IGFET to spread the high field at thedrain pinchoff region and thus reduce the maximum field intensity. TheQSA MOS device includes four mutually self-aligned areas: a narrowpolysilicon gate, shallow-source/drain to eliminate short-channeleffects, deep junctions for high conductance, and specific contacts toafford efficient metal innerconnection.

A need has thus arisen to develop an improved process to produce shortone to two micron channel length devices without short channel V_(T)falloff and reasonable source-drain operating voltage support.

SUMMARY OF THE INVENTION

The present invention is an improved process for fabricating a highperformance LSI device without the undesirable electricalcharacteristics of short channel MOS transistors in such circuits. Theprocess reduces the characteristic problems associated with shortchannel devices having a channel length of one to two microns.

The process includes diffusing a very light concentration of P typematerial, such as boron, to create a very lightly doped P-- substrateregion. The source and drain regions are formed from the diffusion of ahigh concentration of N-type material, such as arsenic, to create an N+region for the source and drain. A lighter concentration of N-typematerial is diffused in the region between the N+ material and the gateto create an N- region to reduce punch-through. A high concentration ofP-type material, such as boron, is implanted at the gate and drain areato form a P region to control the drain field and drain bias, such thatthe fields can be limited to the drains lightly doped area. A lighterconcentration of P-type material is implanted beneath the gate to form aP- region to control the V_(T) falloff for short channel devices.

The concentration of boron at the source-gate area is similar to that inthe double diffused (D²) process of the applicant, but the triplediffused (D³) process of the present invention does not require the hightemperature drive because of the shallow and lightly dopedN-source-drain implant. The triple diffusion process of the presentinvention is a highly localized process in which the special featuresare in effect independently adjustable. The N+ junction depth (X_(j))can be driven independently. In addition, the N- junction depth (X_(j))and length are adjustable according to device specifications through theundercutting of the polysilicon gate.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention of theadvantages and features thereof, reference is now made to theaccompanying Detailed Description taken in conjunction with thefollowing figures in which:

FIG. 1 is a cross sectional view of a transistor device structure of thepresent invention;

FIG. 2 is a profile of the device structure of FIG. 1 taken along thelines 2--2 in FIG. 1;

FIG. 3 illustrates the shallow boron implant step in the process;

FIG. 4 illustrates the device structure after the process steps ofpolygate photo resist patterning, plasma etching of the oxide andpolysilicon, and undercutting of the polysilicon;

FIG. 5 illustrates the diffusion of arsenic impurity material to thedevice structure;

FIG. 6 illustrates a light diffusion of arsenic material and boronimplant; and

FIG. 7 illustrates the process of driving the arsenic and boronimpurities into the substrate and oxidizing the surface.

DETAILED DESCRIPTION

FIG. 1 illustrates one FET of a large scale integrated circuitfabricated in accordance with the process of the present invention, theFET device being generally identified by the reference numeral 10. Thesubstrate region 12 of the device is a silicon material lightly dopedwith a P-type material, such as boron, and designated as a P-- region. Agate 14 is separated from the silicon substrate 12 by a layer of silicondioxide 15. A channel region 16 above the P-- region 12 and below thegate 14 is slightly heavier doped with a P-type material than substrate12 and is designated as a P- region. A source 18 and drain 20 are formedby heavily doping a region of the substrate 12 on opposite sides of thegate 14 with an N-type material and designated as an N+ region.

Two first regions 22 and 24 are doped with P-type material in a greaterconcentration than channel region 16, and designated as a P region,extending from beneath the edges of the gate 14 downwardly to theboundary of the N+ source 18 and drain 20. The P-type material implantedin regions 22 and 24 supports the shallow punchthrough and V_(T)falloff.

Two second regions 26 and 28 are lightly doped with an N-type material,such as arsenic, to create shallow N- regions between the gate 14 andthe N+ source 18 and drain 20. The N- regions 26 and 28 reduce thedepletion at the gate 14-drain 20 region and also reduce the overlap ofthe gate and drain, enhancing the effect of the double diffused P-typematerial in regions 22 and 24.

FIG. 2 illustrates a profile of the concentration of N and P-typeimpurities implanted into the device 10, taken along the line 2--2 ofFIG. 1. The heaviest implantation of N-type material is found in thesource and drain regions 18 and 20. The regions 26 and 28 are lightlydoped with an N-type material to form N- regions between the N+ regions18 and 20 and the edges of the gate region 14. The profile of theimpurity concentration in the channel region, located directly beneaththe gate 14 includes the P-channel region 16 beneath the center of thegate 14 and extending to regions 22 and 24 on either side, which regionscontain a greater concentration of P-type material.

The process of manufacturing the field effect transistor 10 begins withoxidizing the upper surface of the silicon substrate 12. As illustratedin FIG. 3, a layer of silicon dioxide 40, approximately 300 angstromsthick, is grown atop the substrate 12. A first implantation 42 of aP-type material, such as boron, occurs after the formation of thesilicon dioxide layer 40. The boron implantation occurs at an intensityof about 2×10⁴ boron ions/cm² at an energy level of 40 Kev in accordancewith known ion implantation techniques. The first diffusion 42 of P-typematerial supports the shallow punchthrough and adjustment of the V_(T)falloff.

The next process steps for manufacturing the FET 10 is the beginning ofthe formation of the polysilicon gate .[.14.]. with the deposition of alayer .Iadd.14 .Iaddend.of polysilicon material with a depth of about5,000 angstroms, using known deposition techniques. The layer ofpolysilicon material is next implanted with phosphorous, an N-typematerial. The layer of polysilicon material implanted with phosphorousis then oxidized .[.with.]. .Iadd.to form .Iaddend.a layer .Iadd.46.Iaddend.of silicon dioxide .Iadd.hereinafter to be termed a polyoxidelayer .Iaddend.approximately 1,500 angstroms in thickness.

FIG. 4 illustrates the next three steps in the process of manufacturingthe FET device 10. The first step is the covering of the polysilicon.[.gate.]. .Iadd.layer .Iaddend.14 with a layer of photoresist 44,.Iadd.patterning the resist in the usual fashion to essentially definethe gate electrode portion .Iaddend.followed by a wet etching of thepolysilicon oxide layer 46 and the plasma etching of the layer ofpolysilicon .[.of gate.]. 14 beneath it. The next step is theundercutting of the polysilicon layer of gate 14 beneath the polyoxidelayer 46 .Iadd.to achieve the stage shown in FIG. 4.Iaddend.. Thedistance the polysilicon layer is undercut allows for the adjustment ofthe N- regions 26 and 28 (FIG. 1). The photoresist layer 44 is thenstripped, using conventional techniques.

FIG. 5 illustrates the implantation step 50 of an N-type material, suchas arsenic, for forming the heavily doped N+ regions 18 and 20 for thesource and drain of the FET 10. The energy of the arsenic ion isselected so as to penetrate only through the portions not covered by the.[.polysilicon oxide.]. .Iadd.polyoxide .Iaddend.layer 46. An intensityof about 2×10¹⁶ arsenic ions/cm² with an energy level of 60 Kev isselected, using known ion implantation techniques. Following theimplantation of the arsenic, the .[.silicon dioxide.]. .Iadd.polyoxide.Iaddend.layer 46 is etched away.

FIG. 6 illustrates an implantation step 52 of N-type material, such asarsenic, as indicated by the solid arrows, for forming regions 26 and28. The intensity of the arsenic ions is 1×10¹³ arsenic ions/cm² with anenergy level of 60 Kev. The implantation step 52 provides a lightlydoped area forming the N- region 26 and 28, which are between gateregion 14, and a heavier N+ region 18 and 20 for the source and drain. Asecond implantation 54 of P-type material, such as boron, is indicatedby the dashed arrow in FIG. 6. An intensity of about 5×10¹² boronions/cm² with an energy level of 35 Kev is used in accordance with knownion implantation techniques. The triple diffusion process is theimplantation step 50 to form N+ regions 18 and 20, the implantation step52 to form N- regions 26 and 28, and the implantation step 54 to formthe P regions 22 and 24.

FIG. 7 illustrates the next process step of thermally oxidizing theupper layer of the .[.FET 10, and the.]. .Iadd.silicon wafer to formlayer 32. The .Iaddend.oxidation process drives the boron .[.D² .].implantation to greater depths within the substrate 12. Following.Iadd.selective removal of portions of layer 32 where the contacts areto be provided, there follows .Iaddend.a metalization process to formthe contacts, .Iadd.and thus .Iaddend.the metal oxide semiconductor FETtransistor structure 10 has been constructed.

The process described above for manufacturing the metal oxidesemiconductor FET 10 has a number of advantages over previous deviceprocesses. The principle advantage is the individual adjustment ofspecial features of the device 10. The substrate 12 with it lightlydoped P-- region has high resistivity. The N+ regions of the source 18and drain 20 can be driven independently to adjust the penetration ofthe N+ region into the substrate. The double diffusion of the boron doesnot need as long a drive time as in previous processes, since the N-region is a lightly doped region of N-type material, and the doublediffused boron can be driven at the same time the N- material is driven.The N- regions at the edge of gate 14 are adjustable according tomanufacturer's specifications. As indicated above, the N- region can becontrolled by the undercutting of the polysilicon gate 14. Finally,there is a small overlap capacitance between the polysilicon gate 14 andthe source/drain in the semiconductor device 10 made in accordance withthe present invention.

In one semiconductor device 10 manufactured in accordance with thepresent invention, the gate 14 had a length of approximately 1.5microns, the source and drain N+ region had a X_(j) dimension of 0.7microns, the N- regions have a X_(j) dimension of approximately 1.5microns, and the P-type regions 22 and 24 had a thickness ofapproximately 0.3 microns.

Although a preferred embodiment of the invention has been illustrated inthe accompanying Drawings and described in the foregoing DetailedDescription, it will be understood that the invention is not limited tothe embodiments disclosed herein, but they are capable of numerousrearrangements, modifications and substitution without departing fromthe spirit of the invention.

What is claimed is:
 1. A method for manufacturing a metal oxidesemiconductor transistor device comprising:providing a semiconductorsubstrate of a first conductivity type; forming a first insulating layerof silicon dioxide on an active surface of the substrate; implantingions of a first conductivity type into said substrate; depositing alayer of polysilicon on said first insulating layer; implanting ions ofa second conductivity type through said polysilicon layer; growing asecond region of silicon dioxide, said silicon dioxide region beinggrown over said polysilicon layer; placing a photoresistive mask oversaid second oxidation layer for forming a gate of the semiconductordevice; etching a predetermined portion of said second oxidation layer;plasma etching said polysilicon layer; removing a predetermined portionof said polysilicon layer underneath said second silicon dioxide layer;.[.etching said second layer of silicon dioxide;.]. stripping saidphotoresist area from said second oxidation layer; implanting ions ofthe second conductivity type; .[.implanting ions of the firstconductivity type;.]. etching said second layer of silicon dioxideoverhanging said polysilicon gate layer; .[.etching said first layer ofsilicon dioxide surrounding said polysilicon gate layer;.]. implantingions of said first conductivity type; implanting ions of said secondconductivity type; diffusing the implanted ions into said substrate; andoxidizing the active surface of said substrate, including saidpolysilicon gate.
 2. The method of making a metal oxide semiconductortransistor device of claim 1, wherein the implantation of ions of thefirst conductivity type are boron ions and the implantation of ions ofthe second conductivity type are arsenic ions. .Iadd.
 3. A method forforming an MOS transistor comprising the steps ofproviding a siliconwafer of p-type, forming a gate oxide layer over the top surface of thewafer, implanting acceptor ions non-selectively into the top surface ofthe wafer, depositing a polysilicon layer over the gate oxide layer,oxidizing the top surface of the polysilicon layer to form a polyoxidelayer, depositing a layer of photoresist over the polysilicon layer andpatterning the photoresist to leave a selected portion overlying thepolyoxide layer, using a selected portion of the photoresist whileetching the polyoxide layer and the polysilicon layer and undercuttingthe polyoxide layer a prescribed amount, implanting donor ionsselectively into the wafer using the polyoxide layer and the polysiliconlayer as a mask, removing the polyoxide layer from the top surface ofthe polysilicon layer, implanting donor and acceptor ions selectivelyinto the wafer using the polysilicon layer as a mask, and heating thewafer for diffusing the implanted acceptor ions deeper into the waferthan the implanted donor ions. .Iaddend. .Iadd.
 4. The process of claim3 in which the acceptor ions implanted are boron ions and the donor ionsimplanted are arsenic ions. .Iaddend. .Iadd.5. The process of claim 3which includes the further steps of providing separately a gateconnection to the polycrystalline layer, and source and drainconnections to the donor-rich surface layer portions adjacent to theacceptor-rich region underlying the polycrystalline layer. .Iaddend..Iadd.6. The method of claim 3 wherein the implantation of ions of thefirst conductivity type are boron ions and the implantation of ions ofthe second conductivity type are arsenic ions. .Iaddend. .Iadd.7. Amethod for manufacturing a metal oxide semiconductor transistor devicecharacterized in that it comprises the following steps:providing asemiconductor substrate (12) of a first conductivity type, forming afirst insulating layer (40) of silicon dioxide on an active surface ofthe substrate, implanting (42) ions of a first conductivity type intosaid substrate, depositing a layer (14) of polysilicon on said firstinsulating layer, implanting ions of a second conductivity type in saidpolysilicon layer, growing a second region (46) of silicon dioxide, saidsilicon dioxide region being grown over said polysilicon layer, placinga photoresistive mask (44) over said second silicon dioxide regionetching a predetermined portion of said second dioxide region and plasmaetching said polysilicon layer; to leave a double layer of silicondioxide and polysilicon longer than desire for the gate, removing apredetermined portion of said polysilicon layer underneath said secondsilicon dioxide layer to realize the polysilicon gate (14) stripping thephotoresist mask from said second silicon dioxide layer leaving aportion of the second layer of silicon dioxide overhanging saidpolysilicon gate implanting (50) ions of the second conductivity type byusing said second layer of silicon dioxide as a mask for forming heavilydoped regions etching said second layer (46) of silicon dioxideoverhanging said polysilicon gate layer implanting (52) ions of saidsecond conductivity type for forming lightly doped regions between thegate region and the heavily doped regions implanting (54) ions of saidfirst conductivity type for forming doped regions under the edges of thegate diffusing the implanted ions into said substrate, and oxidizing theactive surface of said substrate, including said polysilicon gate..Iaddend.